CMOS devices with schottky source and drain regions

ABSTRACT

A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device are reduced by forming the PMOS device over a semiconductor layer having a low valence band.

TECHNICAL FIELD

This invention relates generally to semiconductor devices, and moreparticularly to manufacturing processes of metal-oxide-semiconductor(MOS) devices with Schottky source and drain regions.

BACKGROUND

Complementary metal-oxide-semiconductor (CMOS) devices have been thebasic logic building block in the digital-dominant world for decades.Device dimensions have been continuously reduced in order to achievehigher performance as well as higher packing density. When the CMOSdevices become increasingly smaller, the device drive currents becomeincreasingly greater. The greater drive currents require that thesource/drain resistances R_(SD) be small. In conventional MOS devices,R_(SD) is related to the doping concentration in the source/drainregions. Therefore, small R_(SD) were achieved by increasing the dopantconcentrations in source/drain extension regions and source/drainregions. In the past, the reduction in R_(SD) could not meet therequirement of the increase in drive currents.

Schottky source/drain regions and source/drain extension regions, whichincluded metals for forming Schottky contacts with the adjoiningsemiconductor materials, are thus explored for lowering R_(SD). Theadvantageous features of Schottky barrier MOS (SBMOS) devices includelow fabrication cost, low thermal budget for the source and drainformation, improved carrier transport, and high scalability. However,high barrier heights between the source/drain regions and the adjoiningsemiconductor materials often incur high series of resistances, andhence the improvement in the drive currents is limited. Therefore, lowSchottky barriers are necessary for obtaining high drive currents. Inthe conventional single-metal scheme in which a single metal (typicallymid-gap metal) is used for forming Schottky source/drains of both p-typeMOS (PMOS) and n-type MOS (NMOS) devices, the barrier heights of theSchottky junctions of NMOS devices may be reduced by increasing thedopant concentration of the semiconductor materials adjoining thejunctions. However, for PMOS devices, the reduction in barrier junctionheights quickly saturates the increase in boron concentration. As such,the conventional single metal scheme cannot provide adequately lowSchottky barriers.

The metals used in the source/drain regions preferably have band-edgework functions, that is, for an NMOS device, the work function of therespective metal needs to be close to the conduction band of theadjoining semiconductor material. For a PMOS device, the work functionof the respective metal needs to be close to the valence band of theadjoining semiconductor material. To meet this requirement, a dual-metalscheme is used for forming NMOS and PMOS devices. For example, ErSi andPtSi have been used in Schottky source/drain regions of NMOS and PMOS,respectively. FIG. 1 illustrates a conventional Schottky CMOS structure,which includes NMOS device 2 and PMOS device 4. NMOS device 2 includesSchottky source/drain extensions 6 and source/drain regions 8, whilePMOS device 4 includes Schottky source/drain extensions 10 andsource/drain regions 12. Schottky source/drain extensions 6 include afirst metal with a low work function, such as ErSi, while Schottkysource/drain extensions 10 include a second metal with a high workfunction, such as PtSi. Since both the first and the second metals haveband-edge work functions, the barrier heights for both PMOS and NMOSdevices are low.

The conventional dual-metal scheme suffers drawbacks, however. Schottkysource/drain extensions 6 and 10 need to be separately formed, thusincurring a higher cost. Thus, novel CMOS structures and the methods forforming the same that may take advantage of improved performance withoutincreasing manufacturing cost are needed.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, a semiconductorstructure includes a semiconductor substrate, and an NMOS device at asurface of the semiconductor substrate, wherein the NMOS devicecomprises a Schottky source/drain extension region; and a PMOS device atthe surface of the semiconductor substrate, wherein the PMOS devicecomprises a source/drain extension region comprising only non-metalmaterials.

In accordance with another aspect of the present invention, asemiconductor structure includes a semiconductor substrate, and an NMOSdevice at a surface of the semiconductor substrate. The NMOS deviceincludes a first gate dielectric on the semiconductor substrate; a firstgate electrode on the first gate dielectric; a first gate spacer on asidewall of the first gate electrode and a sidewall of the first gatedielectric; and a first source/drain extension region having an inneredge substantially aligned to an outer edge of the first gate spacer,wherein the first source/drain extension region is a metal silicideregion having a Schottky contact with the semiconductor substrate. Thesemiconductor structure further includes a PMOS device at the surface ofthe semiconductor substrate. The PMOS device includes a second gatedielectric on the semiconductor substrate; a second gate electrode onthe first gate dielectric; a second gate spacer on a sidewall of thesecond gate electrode and a sidewall of the second gate dielectric,wherein the second gate spacer is thicker than the first gate spacer; asecond source/drain extension region having an inner edge substantiallyaligned to an edge of the first gate stack, wherein the secondsource/drain extension region has an Ohmic contact with thesemiconductor substrate; a source/drain region adjacent the second gatestack, wherein the source/drain region is substantially aligned to anouter edge of the second gate spacer; and a silicide region on thesecond source/drain region, wherein the first source/drain extensionregion and the silicide region comprise same metals.

In accordance with yet another aspect of the present invention, asemiconductor structure includes a semiconductor substrate; an NMOSregion in the semiconductor substrate, wherein the NMOS region onlycomprises a base semiconductor substrate having a first valence band; aPMOS region in the semiconductor substrate, wherein the PMOS regioncomprises an additional semiconductor layer on the base semiconductorsubstrate, and wherein the additional semiconductor layer has a secondvalence band lower than the first valence band; and an NMOS device inthe NMOS region and a PMOS device in the PMOS region. The NMOS deviceincludes a first gate stack on the base semiconductor substrate and afirst Schottky source/drain extension region adjacent the first gatestack. The PMOS device includes a second gate stack over the additionalsemiconductor substrate and a second Schottky source/drain extensionregion adjacent the second gate stack, wherein the second Schottkysource/drain extension region has a bottom surface lower than a topsurface of the additional semiconductor layer, and wherein the first andthe second Schottky source/drain extension regions comprise same metals.

In accordance with yet another aspect of the present invention, a methodfor forming a semiconductor structure includes providing a semiconductorsubstrate; forming an NMOS device at a surface of the semiconductorsubstrate, the NMOS device comprising a Schottky source/drain extensionregion; and forming a PMOS device at the surface of the semiconductorsubstrate, wherein the PMOS device comprises a source/drain extensionregion comprising only non-metal materials.

In accordance with yet another aspect of the present invention, a methodfor forming a semiconductor structure includes providing a semiconductorsubstrate and forming an NMOS device and a PMOS at a surface of thesemiconductor substrate. The step of forming the NMOS device includesforming a first gate stack on the semiconductor substrate; forming athick spacer on a sidewall of the first gate stack; implanting an n-typeimpurity to form a first source/drain region; thinning the thick spacerto form a thin spacer; and reacting a top portion of the semiconductorsubstrate adjacent the thin spacer to form a Schottky source/drainextension region. The step of forming a PMOS device includes forming asecond gate stack on the semiconductor substrate; implanting a p-typeimpurity to form a source/drain extension region; forming a spacer on asidewall of the second gate stack; implanting a p-type impurity to forma second source/drain region; and reacting a top portion of the secondsource/drain region to form a source/drain silicide region, wherein theSchottky source/drain extension region of the NMOS device and thesource/drain silicide region of the PMOS device are simultaneouslyformed.

In accordance with yet another aspect of the present invention, a methodfor forming a semiconductor structure includes providing a basesemiconductor substrate comprising a PMOS region and an NMOS region,wherein the base semiconductor substrate has a first valence band; andforming an additional semiconductor layer only on the base semiconductorsubstrate in the PMOS region, wherein the additional semiconductor layerhas a second valence band lower than the first valence band. The methodfurther includes forming an NMOS device in the NMOS region, whichcomprises forming a first gate stack on the base semiconductorsubstrate; and forming a first Schottky source/drain extension regionadjacent the first gate stack. The method further includes forming aPMOS device in the PMOS region, which comprises forming a second gatestack over the additional semiconductor substrate; and forming a secondSchottky source/drain extension region adjacent the second gate stack,wherein the second Schottky source/drain extension region has a bottomsurface lower than a top surface of the additional semiconductor layer,and wherein the step of forming the first and the second Schottkysource/drain extension regions are simultaneously performed.

The advantageous features of the present invention include reducedSchottky barrier layers for both PMOS and NMOS devices without incurringthe high cost of the dual-metal scheme.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a conventional complementary Schottkymetal-oxide-semiconductor (CMOS) structure formed using a dual-metalscheme;

FIGS. 2 through 7 are cross-sectional views of intermediate stages inthe manufacturing of a first embodiment of the present invention; and

FIGS. 8 through 12 are cross-sectional views of intermediate stages inthe manufacturing of a second embodiment of the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

Experiments have been performed to study the behavior of p-typemetal-oxide-semiconductor (PMOS) and n-type metal-oxide-semiconductor(NMOS) devices. In the experiment, a single-metal scheme is used,wherein a mid-gap metal with a work function of about 4.5 eV is used toform Schottky source/drain extension regions for both PMOS and NMOSdevices. These experiment results have revealed that compared toconventional CMOS devices having implanted source/drain extensionregions, the drive currents of NMOS devices formed using thesingle-metal scheme are improved by about 8 percent to about 10 percent,while the drive currents of PMOS devices formed using the single-metalscheme are degraded by about 6 percent. However, the degradation in thedrive currents of PMOS devices cannot be compensated for by increasingboron concentrations in the semiconductor substrates adjacent theSchottky junctions. The preferred embodiments of the present inventionare provided to address this finding.

FIGS. 2 through 7 illustrate a first embodiment of the presentinvention. FIG. 2 illustrates substrate 30 comprising two regions,region 100 for forming an NMOS device and region 200 for forming a PMOSdevice. Shallow trench isolation (STI) regions are formed in substrate30 to isolate device regions 100 and 200. Substrate 30 is preferably abulk silicon substrate, although other commonly used materials andstructures such as silicon-germanium (SiGe), silicon-on-insulator (SOI),SiGe-on-insulator, and strained-silicon-on-insulator may also be used. Agate stack including gate dielectric 104 and gate electrode 106 isformed in NMOS region 100. Similarly, a gate stack including gatedielectric 204 and gate electrode 206 is formed in PMOS region 200. Asis known in the art, hard masks (not shown) may be formed on the gatestacks for process reasons, wherein the hard masks may include siliconnitride.

Source/drain extension regions 208, or often referred to as LDD regions208, are then formed. Preferably, photo resist 110 is formed andpatterned to mask NMOS region 100. PMOS region 200 is then implantedwith a p-type impurity such as boron, forming LDD regions 208. Photoresist 110 is then removed. In the preferred embodiment, no LDD regionsare formed in NMOS region 100. In other embodiments, LDD regions 108 areformed. Similarly, during the n-type impurity implantation, PMOS region200 is masked by a photo resist (not shown), and an implantation of ann-type impurity is performed to NMOS region 100, forming LDD regions108. In subsequently drawings, LDD regions 108 are not shown.

FIG. 3 illustrates the formation of spacers 114 and 214 in regions 100and 200, respectively. As is known in the art, the formation of spacers114 and 214 preferably includes depositing one or more dielectriclayer(s) and etching the dielectric layer(s). The remaining portions ofthe dielectric layer(s) become spacers. The deposition of the dielectriclayer(s) includes commonly used techniques, such as plasma enhancedchemical vapor deposition (PECVD), low-pressure chemical vapordeposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD),and the like. The resulting spacers 114 and 214 each may comprise asingle layer or more than one layer, such as a silicon nitride layer ona silicon oxide layer. In alternative embodiments (not shown), spacers114 and 214 each include a thin spacer (not shown) on the sidewall ofthe respective gate stacks, and a dispensable spacer (not shown) on thesidewall of the respective thin spacer.

FIG. 4 illustrates the formation of source/drain regions 120 and 220. Asis known in the art, source/drain regions 120 and 220 may be recessed inor elevated above substrate 30 (using, e.g., epitaxially grown regions).In the preferred embodiment, source/drain regions 120 and 220 are formedby implanting impurities into semiconductor substrate 30. Gateelectrodes 106 and 206 are preferably implanted simultaneously with theimplantation of the respective source/drain regions to reduce sheetresistance. When region 100 is implanted with an n-type impurity, region200 is masked by a photo resist (not shown). Similarly, when region 200is implanted with a p-type impurity, region 100 is masked by a photoresist (not shown).

In alternative embodiments, SiGe stressors (not shown) are formed forthe PMOS device. Preferably, a photo resist (not shown) is formed tocover NMOS region 100. Recesses are formed in substrate 30 along outsideedges of spacers 214, preferably by etching. The SiGe stressors are thenformed in the recesses, preferably by an epitaxial growth. The photoresist is then removed.

FIG. 5 illustrates the thinning of sidewall spacers 114. Mask 222 isformed to cover PMOS region 200, wherein mask 222 may include photoresist or other commonly used mask materials. In an exemplary embodimentwherein sidewall spacers 114 include a silicon nitride layer on a lineroxide layer, the silicon nitride layer is first stripped. The lineroxide layer is then etched, preferably by a dry etching to removehorizontal portions of the liner oxide layer, hence the vertical portionforms thin spacer 124. In the case spacers 114 each include adispensable spacer on a thin spacer, the dispensable spacers areremoved, leaving the thin spacers. Mask 222 is then removed.

Referring to FIG. 6, a silicidation process is performed. A thin metallayer is blanket formed over the structure formed in preceding steps.The substrate is then heated, which causes silicon to react with themetal where contacted. After the reaction, a layer of metal silicide isformed between substrate 30 and the metal. The un-reacted metal isselectively removed through the use of an etchant that attacks the metalbut does not attack silicide. In the resulting structure, Schottkysource/drain extension regions 126 are formed in NMOS region 100, whilesource/drain silicide regions 226 are formed in PMOS region 200.

In the preferred embodiment, the metal used for the silicidation processhas a low work function, for example, lower than about 4.25 eV. Morepreferably, the metal has a band-edge work function of close to theconduction band of semiconductor substrate 30. Accordingly, the barrierheight for the resulting NMOS device is lowered, and the drive currentis increased. Alternatively, mid-gap metals are used. The exemplarymetals include erbium, holmium, titanium, hafnium, zirconium, cobalt,nickel, and combinations thereof. On the other hand, since source/drainextension regions 208 are formed by implantation, the degradation to thePMOS device, as discussed in preceding paragraphs, is eliminated.

FIG. 7 illustrates the formation of contact etch stop layers (CESL) 128and 228. In an embodiment, CESLs 128 and 228 are portions of a samecontinuous layer, which preferably has a tensile stress. Advantageously,with thin spacers 124, the tensile stress applied to the channel regionof the NMOS device is high. On the other hand, due to thick spacers 214,the detrimental tensile stress applied to the channel region of the PMOSdevice is low. In alternative embodiments, CESL 128 has an inherenttensile stress, while CESL 228 has an inherent compressive stress.

FIGS. 8 through 12 illustrate a second embodiment of the presentinvention, wherein both PMOS and NMOS devices have Schottky source/drainextension regions. To simplify the discussion, like reference numeralsin the first embodiment are used to reference like elements in thesecond embodiment, unless specified otherwise. Referring to FIG. 8, basesemiconductor substrate 30 is provided, which includes NMOS region 100and PMOS region 200. Base semiconductor substrate 30 preferablycomprises silicon, although other commonly used semiconductor materialsmay be used. In PMOS region 200, SiGe layer 240 is formed on basesemiconductor substrate 30, followed by the formation of silicon layer242 on SiGe layer 240. SiGe layer 240 and silicon layer 242 may beformed by epitaxial growths. Alternatively, SiGe layer 240 may be formedby implanting germanium into base silicon substrate 30. In an exemplaryembodiment, SiGe layer 240 has a thickness of less than about 300 Å,while silicon layer 242 has a thickness of between about 50 Å and about200 Å. Preferably, silicon layer 242 is thin enough, so that in thesubsequent silicidation process, silicon layer 242 will fully react witha metal, and the underlying SiGe layer 240 will react with the metal, atleast partially, and more preferably entirely.

In alternative embodiments, SiGe layer 240 may be replaced by othermaterials having lower valence bands than the valence bands of siliconlayer 242 and base semiconductor substrate 30.

FIG. 9 illustrates the formation of gate stacks 102 and 202,source/drain regions 120 and 220, and spacers 114 and 214. The processdetails are essentially the same as in the first embodiment, and thusare not repeated herein. Preferably, no implantations are performed toform LDD regions in both regions 100 and 200, although they can beformed.

In FIG. 10, spacers 114 and 214 are thinned to form thin spacers 124 and224, respectively. Subsequently, a silicidation is performed to formSchottky source/drain extension regions 144 and 244, forming structuresas shown in FIGS. 11A and 11B. The metal used for the silicidationpreferably has a work function of between the conduction band of basesemiconductor substrate 30 and the valence band of SiGe layer 240. Theappropriate metals include erbium, platinum, nickel, cobalt, ytterbium,magnesium, aluminum, titanium, and combinations thereof. In thepreferred embodiment, SiGe layer 240 fully reacts with the metal duringthe silicidation process, as illustrated in FIG. 11A. In otherembodiments, as shown in FIG. 11B, only a top portion of SiGe layer 240reacts with the metal to form germano-silicide, while the bottom portionof SiGe layer 240 is not reacted. In both FIGS. 11A and 11B, theSchottky source/drain extension regions 144 and 244 include silicidelayers 144 ₁ and 244 ₁ on germano-silicide layers 144 ₂ and 244 ₂,respectively.

It is appreciated that SiGe has a lower valence band than silicon. Theband gap between the valence band of SiGe and the conduction band ofsilicon is accordingly lower than the band gap of silicon. At interfacesbetween SiGe layer 240 and the respective Schottky source/drainextension region 244, the barrier height is lowered. In this embodiment,even though a single-metal scheme is used to form Schottky source/drainextension regions for both PMOS and NMOS devices, with an appropriatemetal selected, at least one of the NMOS and PMOS devices, and may beboth, can have lowered Schottky barrier heights.

In subsequent process steps, CESLs 128 and 228 are formed. Since boththe PMOS and NMOS devices have thin spacers, CESL 228 preferably has acompressive stress, and CESL 128 preferably has a tensile stress.

The embodiments of the present invention have several advantageousfeatures. By using the single-metal scheme to form Schottky source/drainextension regions, the cost is lower than the dual-metal scheme, whilethe performance of the CMOS devices is not sacrificed. The formation ofthe Schottky source/drain extension regions is integrated with theformation of thin spacers to further improve the performance of CMOSdevices.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. Moreover, thescope of the present application is not intended to be limited to theparticular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

1. A semiconductor structure comprising: a semiconductor substrate; anNMOS device at a surface of the semiconductor substrate, the NMOS devicecomprising a Schottky source/drain extension region; and a PMOS deviceat the surface of the semiconductor substrate, wherein the PMOS devicecomprises a source/drain extension region comprising only non-metalmaterials.
 2. The semiconductor structure of claim 1, wherein theSchottky source/drain extension region comprises a metal silicide. 3.The semiconductor structure of claim 1, wherein the NMOS device furthercomprises a first gate stack on the semiconductor substrate and a firstgate spacer on a sidewall of the first gate stack, and the PMOS devicefurther comprises a second gate stack on the semiconductor substrate anda second gate spacer on a sidewall of the second gate stack, and whereinthe second gate spacer is thicker than the first gate spacer.
 4. Thesemiconductor structure of claim 3 further comprising a tensile contactetch stop layer extending from over the NMOS device to over the PMOSdevice.
 5. The semiconductor structure of claim 3, wherein the Schottkysource/drain extension region has an inner edge substantially aligned toa sidewall of the first gate spacer.
 6. The semiconductor structure ofclaim 1, wherein the PMOS device further comprises a source/drain regionadjoining the source/drain extension region, and a source/drain silicideregion on the source/drain region, and wherein the source/drain silicideregion and the Schottky source/drain extension region of the NMOS devicecomprise same metals.
 7. The semiconductor structure of claim 1, whereina metal in the Schottky source/drain extension region has a workfunction close to a conduction band of the semiconductor substrate.
 8. Asemiconductor structure comprising: a semiconductor substrate; an NMOSdevice at a surface of the semiconductor substrate, the NMOS devicecomprising: a first gate dielectric on the semiconductor substrate; afirst gate electrode on the first gate dielectric; a first gate spaceron a sidewall of the first gate electrode and a sidewall of the firstgate dielectric; and a first source/drain extension region having ainner edge substantially aligned to an outer edge of the first gatespacer, wherein the first source/drain extension region is a metalsilicide region having a Schottky contact with the semiconductorsubstrate; and a PMOS device at the surface of the semiconductorsubstrate, the PMOS device comprising: a second gate dielectric on thesemiconductor substrate; a second gate electrode on the second gatedielectric; a second gate spacer on a sidewall of the second gateelectrode and a sidewall of the second gate dielectric, wherein thesecond gate spacer is thicker than the first gate spacer; a secondsource/drain extension region having an inner edge substantially alignedto an edge of the first gate stack, wherein the second source/drainextension region has an Ohmic contact with the semiconductor substrate;a source/drain region adjacent the second gate stack, wherein thesource/drain region is substantially aligned to an outer edge of thesecond gate spacer; and a silicide region on the second source/drainregion, wherein the first source/drain extension region and the silicideregion comprise same metals.
 9. The semiconductor structure of claim 8further comprising a contact etch stop layer having a tensile stressextending from over the NMOS device to over the PMOS device.
 10. Thesemiconductor structure of claim 8, wherein the first source/drainextension region comprises a metal having a work function of lower thanabout 4.25 eV.
 11. A semiconductor structure comprising: a semiconductorsubstrate; an NMOS region in the semiconductor substrate, wherein theNMOS region only comprises a base semiconductor substrate having a firstvalence band; a PMOS region in the semiconductor substrate, wherein thePMOS region comprises an additional semiconductor layer on the basesemiconductor substrate, and wherein the additional semiconductor layerhas a second valence band lower than the first valence band; an NMOSdevice in the NMOS region, the NMOS device comprising: a first gatestack on the base semiconductor substrate; a first Schottky source/drainextension region adjacent the first gate stack; and a PMOS device in thePMOS region, the PMOS device comprising: a second gate stack over theadditional semiconductor layer; a second Schottky source/drain extensionregion adjacent the second gate stack, wherein the second Schottkysource/drain extension region has a bottom surface lower than a topsurface of the additional semiconductor layer, and wherein the first andthe second Schottky source/drain extension regions comprise same metals.12. The semiconductor structure of claim 11, wherein the first Schottkysource/drain extension region comprises a silicide, and the secondSchottky source/drain extension region comprises a germano-silicide. 13.The semiconductor structure of claim 11, wherein the bottom surface ofthe second Schottky source/drain extension region is between the topsurface and a bottom surface of the additional semiconductor layer. 14.The semiconductor structure of claim 11, wherein the bottom surface ofthe second Schottky source/drain extension region is level with or lowerthan a bottom surface of the additional semiconductor layer.
 15. Thesemiconductor structure of claim 11, wherein the base semiconductorsubstrate is a silicon substrate, the additional semiconductor layer isa silicon-germanium layer, and wherein the second Schottky source/drainextension region comprises a metal silicide layer on a metalgermano-silicide layer.
 16. The semiconductor structure of claim 11further comprising: a first contact etch stop layer having a tensilestress over the NMOS device; and a second contact etch stop layer havinga compressive stress over the PMOS device.
 17. A method for forming asemiconductor structure, the method comprising: providing asemiconductor substrate; forming an NMOS device at a surface of thesemiconductor substrate, the NMOS device comprising a Schottkysource/drain extension region; and forming a PMOS device at the surfaceof the semiconductor substrate, wherein the PMOS device comprises asource/drain extension region comprising only non-metal materials. 18.The method of claim 17, wherein the Schottky source/drain extensionregion is performed simultaneously with the formation of a source/drainsilicide region of the PMOS device.
 19. The method of claim 18, whereinthe step of forming the NMOS device comprises: forming a gate stack onthe semiconductor substrate; forming a thick spacer on a sidewall of thegate stack; implanting an n-type impurity to form a source/drain region;thinning the thick spacer to form a thin spacer; and reacting a topportion of the semiconductor substrate adjacent the thin spacer to formthe Schottky source/drain extension region substantially aligned to anouter edge of the thin spacer.
 20. The method of claim 18, wherein thestep of forming the PMOS device comprises: forming a gate stack on thesemiconductor substrate; implanting a p-type impurity to form asource/drain extension region; forming a spacer on a sidewall of thegate stack; implanting a p-type impurity to form a source/drain region;and reacting a top portion of the source/drain region to form thesource/drain silicide region of the PMOS device, wherein the step ofreacting is performed simultaneously with a step of forming the Schottkysource/drain extension region.
 21. The method of claim 18, wherein theSchottky source/drain extension region has a work function of less thanabout 4.25 eV.
 22. The method of claim 17 further comprising forming acontact etch stop layer over the NMOS device and the PMOS device,wherein the contact etch stop layer has a tensile stress.
 23. The methodof claim 17, wherein the step of forming the NMOS device is free from astep of a source/drain extension implantation.
 24. A method for forminga semiconductor structure, the method comprising: providing asemiconductor substrate; forming an NMOS device at a surface of thesemiconductor substrate comprising: forming a first gate stack on thesemiconductor substrate; forming a thick spacer on a sidewall of thefirst gate stack; implanting an n-type impurity to form a firstsource/drain region; thinning the thick spacer to form a thin spacer;and reacting a top portion of the semiconductor substrate adjacent thethin spacer to form a Schottky source/drain extension region; andforming a PMOS device at the surface of the semiconductor substratecomprising: forming a second gate stack on the semiconductor substrate;implanting a p-type impurity to form a source/drain extension region;forming a spacer on a sidewall of the second gate stack; implanting ap-type impurity to form a second source/drain region; and reacting a topportion of the second source/drain region to form a source/drainsilicide region, wherein the Schottky source/drain extension region ofthe NMOS device and the source/drain silicide region of the PMOS deviceare simultaneously formed.
 25. The method of claim 24, wherein theSchottky source/drain extension region and the source/drain silicideregion comprise a metal having a work function of lower than about 4.25eV.
 26. The method of claim 24, wherein the Schottky source/drainextension region and the source/drain silicide region comprise-a metalhaving a work function close to a conduction band of silicon.
 27. Themethod of claim 24 further comprising forming a contact etch stop layerover the NMOS device and the PMOS device, wherein the contact etch stoplayer has a tensile stress.
 28. The method of claim 24, wherein the stepof forming the NMOS device is free from a step of a source/drainextension implantation.
 29. A method for forming a semiconductorstructure, the method comprising: providing a base semiconductorsubstrate comprising a PMOS region and an NMOS region, wherein the basesemiconductor substrate has a first valence band; forming an additionalsemiconductor layer only on the base semiconductor substrate in the PMOSregion, wherein the additional semiconductor layer has a second valenceband lower than the first valence band; forming an NMOS device in theNMOS region comprising: forming a first gate stack on the basesemiconductor substrate; and forming a first Schottky source/drainextension region adjacent the first gate stack; and forming a PMOSdevice in the PMOS region comprising: forming a second gate stack overthe additional semiconductor layer; and forming a second Schottkysource/drain extension region adjacent the second gate stack, whereinthe second Schottky source/drain extension region has a bottom surfacelower than a top surface of the additional semiconductor layer, andwherein the step of forming the first and the second Schottkysource/drain extension regions are simultaneously performed.
 30. Themethod of claim 29, wherein the bottom surface of the second Schottkysource/drain extension region is between the top surface and a bottomsurface of the additional semiconductor layer.
 31. The method of claim29, wherein the bottom surface of the second Schottky source/drainextension region is level with or lower than a bottom surface of theadditional semiconductor layer.
 32. The method of claim 29, wherein thebase semiconductor substrate is a silicon substrate, the additionalsemiconductor layer is a silicon-germanium layer, and wherein the methodfurther comprises forming a silicon layer on the silicon-germanium layerbefore the step of forming the PMOS device.
 33. The method of claim 29further comprising: forming a first contact etch stop layer having atensile stress over the NMOS device; and forming a second contact etchstop layer having a compressive stress over the PMOS device.